1. Field of the Invention
The present invention generally relates to a bus compatible structure, and more particularly, to a structure compatible with I2C bus and system management (SM) bus.
2. Description of Related Art
I2C bus (inter-IC bus or IC to bus) is usually adopted in computer network communication devices. I2C bus is a two-line serial bus which operates in a master/slave mode. Two-line communication signal lines can be categorized into serial clock lines (SCL) and serial data lines (SDA). The speed of an I2C bus is between 0 Hz and 3.4 MHz. An I2C bus allows multiple devices to operate on the same bus, wherein the master and slave transmit data based on the same clock. Since an I2C bus has only two lines, the slaves can be connected to the bus without any additional logic. System management (SM) bus is provided mostly based on the specification of I2C bus. SM bus is also a two-line serial bus which operates between 10 kHz and 100 kHz. However, SM bus and I2C bus have some different timing characteristics. SM bus requires a specific data holding time, while I2C bus delays its data holding time internally.
SM bus requires a data holding time of 300 ns, while the data holding time of I2C bus can be as low as 0 ns. Since SM bus and I2C bus have different requirements to the data holding time, a problem of incompatible data holding time may be produced when a master adopting I2C bus protocol accesses a slave adopting SM bus protocol. For example, a baseboard management controller in a server usually reads the information of an external slave (for example, an external sensor, power supply, or a backplane) through an I2C bus, but the external slave may adopt the SM bus specification. As a result, the baseboard management controller cannot read the information of the external slave due to the inconsistency in the data holding time thereof. Conventionally, a capacitor is disposed in an I2C bus interface in order to delay the signal transmission of the I2C bus. However, the data holding time of the I2C bus may not be up to the requirement due to load capacitance and signal reflex, and accordingly data access error may be caused.